Chemi-mechanical polishing of semiconductor wafers is useful, at various stages of device fabrication, for planarizing irregular top surface topography, inter alia. For example, in the process of fabricating modern semiconductor integrated circuits, it is necessary to form conductive lines or other structures above previously formed structures. However, prior structure formation often leaves the top surface topography of the silicon wafer highly irregular, with bumps, areas of unequal elevation, troughs, trenches and/or other surface irregularities. As a result of these irregularities, deposition of subsequent layers of materials could easily result in incomplete coverage, breaks in the deposited material, voids, etc., if it were deposited directly over the aforementioned highly irregular surfaces. If the irregularities are not alleviated at each major processing step, the top surface topography of the surface irregularities will tend to become even more irregular, causing further problems as layers stack up in further processing of the semiconductor structure.
Depending upon the type of materials used and their intended purposes, numerous undesirable characteristics are produced when these deposition irregularities occur. Incomplete coverage of an insulating oxide layer can lead to short circuits between metallization layers. Voids can trap air or processing gases, either contaminating further processing steps or simply lowering overall device reliability. Sharp points on conductors can result in unusual, undesirable field effects. In general, processing high density circuits over highly irregular structures can lead to very poor yield and/or device performance.
Consequently, it is desirable to effect some type of planarization, or flattening, of integrated circuit structures in order to facilitate the processing of multi-layer integrated circuits and to improve their yield, performance, and reliability. In fact, all of today's high-density integrated circuit fabrication techniques make use of some method of forming planarized structures at critical points in the fabrication process.
Planarization techniques generally fall into one of several categories: chemical/mechanical polishing techniques; leveling with a filler material then etching back in a controlled environment; and various reflow techniques. Etching techniques can include wet etching, dry or plasma etching, electro-polishing, and ion milling, among others. A few less common planarization techniques exist, such as direct deposition of material into a trench by condensing material from a gaseous phase in the presence of laser light. Most of the differences between modern planarization techniques exist in the points in processing that the different techniques are applied, and in which methods and materials are used.
The present invention is directed to chemi-mechanical polishing process, which generally involves "rubbing" a wafer with a polishing pad in a slurry containing both an abrasive and chemicals. Typical slurry chemistry is KOH (Potassium Hydroxide), having a pH of about 11. Generally, polishing slurry is expensive, and cannot be recovered or reused. A typical silica-based slurry is "SC-1" available from Cabot Industries. Another, more expensive slurry based on silica and cerium (oxide) is Rodel "WS-2000".
Chemi-mechanical polishing is described in U.S. Pat. Nos. 4,671,851, 4,910,155, 4,944,836, all of which patents are incorporated by reference herein. When chemi-mechanical polishing is referred to hereinafter, it should be understood to be performed with a suitable slurry, such as Cabot SC-1.
The current state of the art in dielectric film chemi-mechanical polishing for silicon wafers typically involves the use of more than one polishing pad. For example, two pads are secured into a "stack", which may be termed a "composite polishing pad". The top pad, which performs polishing, is typically stiffer than the more compliant bottom pad, which is mounted to a rotating platen. A pressure sensitive adhesive is typically used to adhere the pads together and to the platen.
FIG. 1. shows a typical technique for chemi-mechanical polishing. A first disc-shaped pad 102 (PAD A) having a layer of pressure sensitive adhesive 104 on its back face is adhered (i.e., mounted; shown exploded) to the front face of a rotating platen 106 (PLATEN). A second disc-shaped pad 108 (PAD B) having a layer of pressure sensitive adhesive 110 on its back face is adhered (shown exploded) to the front face of the first pad 102. The platen 106 is rotated (typically at tens of revolutions per minute), and a metered stream of slurry 112 (shown as dots) from a slurry supply 114 is delivered via a slurry feed 116 to the front face of PAD B.
A silicon wafer 120 is mounted to a carrier 122 and is lightly pressed (flat) against the front surface of PAD B so that irregular topographical formations (on the pad-confronting face of the wafer) sought to be polished are acted upon by the action of PAD B and the slurry. Typically, the pads 102 and 108 and the platen 106 are on the order of 20-30 inches in diameter, the wafer is 4-6 inches in diameter, and polishing is performed in the center 2/3portion of PAD B.
A reservoir 130 contains the platen, pads, carrier, wafer and polishing slurry.
Typical pad materials are: (1) for PAD A, foamed polyurethane; and (2) for PAD B, felt fibrules (fibers), such as polyester felt, stiffened with polyurethane resin. PAD B can also be glass-impregnated plastic. The adhesive backings 104 and 110 for the pads are typically polyurethane based. Generally, it is preferable that PAD B is stiffer than PAD A. In the case that both pads are doped with polyurethane resin, this can be achieved simply by doping PAD B with more polyurethane than PAD A.
Current chemi-mechanical polishing techniques suffer from low polish rates, poor repeatability, and sensitivity to pad use history. Pads must be "conditioned" prior to use, and during use the pads wear and change properties. The pads must be reconditioned after use, which only marginally improves polishing repeatability.
Conditioning the pad is a technique wherein the front face of the pad (e.g., PAD B) is "dressed", in a manner similar to dressing a grinding wheel. The general object is that the wafer-confronting face of the pad being conditioned is made to be planar, prior to use. Generally, such conditioning is performed "off-line", in other words separate from the polishing process.
Despite repeated conditioning of the polishing pads, polish rates may change by 20-50% during the lifetime of the pad, even with the best conditioning techniques. Such a variation introduces an undesirable variable into the polishing process.